1. Field of the Invention
The present invention relates to an image memory suitable for use as an apparatus for transmitting, displaying and accumulating image information, and more specifically to an image processing memory integrated circuit for executing inter-image processing on the basis of addition of a plurality of images.
2. Description of the Prior Art
For a high efficiency encoding of moving images (e.g., television signals), prediction processing is executed between frames or between fields, and differential between the obtained prediction signals and the current signals, that is, the prediction residual signals are coded.
In the moving image coding system termed MPEG (Moving Pictures Expert Group) system standardized by ISO (International Organization for Standardization)/IEC (International Electrotechnical Commission), bidirectional prediction is executed on the basis of frames preceding and succeeding frames to be coded. In the bidirectional prediction, there exist two cases where the prediction signals are formed by adding inter-frame prediction images in the forward direction with respect to time and where the prediction signals are formed by adding inter-frame prediction images in the reverse direction with respect to time.
The frame prediction relationship of the coding on the basis of the bidirectional prediction will be described hereinbelow with reference to FIG. 1.
FIG. 1 shows an example of inter-image prediction including the bidirectional prediction.
In FIG. 1, P denotes a unidirectional prediction frame the past and feature frames. The P frames are arranged for each three frames. Only the P frames are used for prediction. The P frame is predicted on the basis of the preceding P frame, and the B frame is predicted on the basis of both the preceding and succeeding P frames with respect to time.
Since both the preceding and succeeding P frames are necessary for prediction of the B frame, the sequence of the frames to be coded and decoded is changed with respect to each other. That is, in the input image, the P frame after the B frame is coded or decoded in advance of the B frame.
On the other hand, in the interlace signals, there exists the case where the even and odd fields are added to each other as the prediction signals.
When the prediction signals are formed by addition of a plurality of images as described above, the addition of the preceding and succeeding images with respect to time provides the prediction signals suitable for image changes along the time axis. On the other hand, the addition of the even and odd fields provides the prediction signals which can represent a minute motion in the vertical direction. Further, since the quantization error and the noise components can be suppressed by the addition, it is possible to execute more appropriate inter-image prediction.
As an example of the apparatus for adding a plurality of images and then processing the added video signals, a decoding apparatus for decoding image information coded by use of the bidirectional inter-frame prediction will be described hereinbelow with reference to FIG. 2.
FIG. 2 is a block diagram showing an example of the prior art decoding apparatus.
In FIG. 2, compressed image information is inputted through a code input terminal 31 and then given to a variable length decoder 32. In this variable length decoder 32, the variable length codes are returned to the fixed length codes, and the obtained fixed length codes are given to a reverse quantizer 33.
Further, from the variable length decoder 32, address information related to a block to be processed (i.e., a block address) is given to a memory controller 81; prediction mode information is given to two multipliers 63 and 64, respectively; and frame type (P or B) information is given to two switches 36 and 37, respectively.
In the reverse quantizer 33, the values representative of quantization corresponding to the fixed length codes can be obtained, and reproduced DCT (discrete cosine transformation) coefficients are given to a reverse DCT 34.
The reverse DCT 34 processes the reverse transformation of the DCT to reproduce the prediction residual signals. The obtained prediction residual signals are given to a prediction signal adder 35.
The prediction signal adder 35 adds the prediction signals given by an adder 62 to the prediction residual signals to obtain reproduced video signals.
The reproduced video signals are given to an image memory 65 via the switch 36 in the case of the unidirectional prediction frame (P frame). At the same time, the reproduced video signals of the preceding P frame are outputted from the image memory 65, and then given to a block reverse converter 38 via the switch 37. Here, the reason why the reproduced video signals of the P frame are delayed is that the reproduced video signals are transmitted in advance for the inter-image prediction of the B frame.
On the other hand, in the case of the bidirectional prediction frame (B frame), the switches 36 and 37 are changed over, so that the reproduced video signals outputted by the prediction signal adder 35 are given to the block inverse converter 38 as it is.
In the above-mentioned processing, the video signals are inputted and outputted in unit of spatial two-dimensional pixel block (e.g., of 16.times.16 pixels). Therefore, in the block reverse converter 38, the signals in unit of block are returned to signals used in the ordinary raster scanning (usually used for display) and then outputted through a video output terminal 39.
In the image memory 65, the reproduced video signals for one frame (P frame) are stored. The accumulated reproduced video signals are read in unit of block in accordance with the logical address information given by the memory controller 61. The read reproduced video signals are given to an image memory 66, and simultaneously to the multiplier 63 as the reverse direction prediction frame signals predicted on the basis of the succeeding frame with respect to time.
In the image memory 66, the video signals for one frame given by the image memory 65 are stored. Further, the forward direction prediction frame signals predicted on the basis of the preceding frame with respect to time are read from the image memory 66 in accordance with the logical address information given by the memory controller 61. The read frame signals are given to the multiplier 64.
In the multipliers 63 and 64, coefficients K1 and K2 are multiplied, respectively for each block according to the prediction mode. Here, the coefficients K1 and K2 are 0 or more but less than 1, and the addition of both K1 and K2 is 1.
For instance, in the case of only the forward direction prediction, the coefficient K1 of the multiplier 63 is determined to be 0 and the coefficient K2 of the multiplier 64 is determined to be 1. Further, in the case of only the reverse direction prediction, the coefficient K1 of the multiplier 63 is determined to be 1 and the coefficient K2 of the multiplier 64 is determined to be 0. In the case of the average prediction of both, the coefficients K1 and K2 are both 0.5.
The reproduced video signals weighted by the multipliers 63 and 64 as described above are given to the adder 62, respectively. In the adder 62, the two signals given by the multipliers 63 and 64 are added to obtain completed prediction signals. The obtained complete prediction signals are given to the prediction signal adder 35.
Here, the image memory 65 or 66 shown in FIG. 2 is composed of a semiconductor memory such as D-RAM (memory in and from which data can be written and read at any time and which requires memory holding operation).
A semiconductor memory integrated circuit of this type will be described hereinbelow with reference to FIG. 3.
In FIG. 3, an address signal inputted through an address input terminal 51 is given to an address decoder 53 via an address buffer 52. The address signal is usually inputted being divided into two and sequentially in series. For instance, in the case of the memory having 220 addresses, the address is inputted 10 bits by 10 bits as a row address and a column address, respectively.
In the address decoder 53, the transmitted logical address information of the row address and column address is developed into an actual physical address of a memory cell array 12, so that a memory cell corresponding to the physical address can be accessed.
At the write timing, the video signals inputted through the data input terminal 1 are written in designated positions of the memory cell array 12 through an input buffer 2.
At the read timing, the video signals outputted by designated positions of the memory cell array 12 are outputted through a data output terminal 11 via an output buffer 3.
In the case of the high efficiency coding for executing the bidirectional inter-image prediction processing or in the case of the image rate transformation for transforming the number of images per unit time, two images must be processed for each one-image processing. Accordingly, the number of the video signals read from the image memory is twice larger than that of the video signals to be processed.
On the other hand, in the image processing apparatus, although the image memory is usually constructed as an element formed independently from the other elements, since the input and output transfer speed of the D-RAM is not sufficiently high in comparison with the speed of the video signals of moving images, it has been so far necessary to increase the number of the transmission lines in order to read a great number of video signals ( whose number is twice larger than that of the video signals to be processed), thus raising a problem in that the apparatus construction is complicated.
In addition, in the case where the picture motion is compensated for on the precision finer than one pixel (e.g., 1/2 pixels), since the pixels whose number is larger than that of the pixels of the signals to be processed are required, it has been so far necessary to increase the transfer rate of the signals read from the image memory.
Further, in the prior art image memory, even in the case where the video signals are read in the state of two-dimensional pixel block composed of rows and lines (e.g., 16.times.16 pixels), since the address must be designated to at least each row, the large address information is required, with the result that there exists a problem in that the number of the transmission lines increases.